Qualitative models and experimental investigation of chaotic NOR gates and set/reset flip-flops

1. Introduction

Since the 1990s, there has been growing interest in controlling chaotic circuits starting from synchronization [1,2], and leading to logical circuits [3]. Constructions of chaotic logical circuits mainly employ the usual circuit elements such as resistors, capacitors and inductors, and a less common component called a nonlinear resistor. The most well-known nonlinear resistor is Chua’s diode, invented by Leon Chua in 1983 and used as an integral element in Chua’s circuit [4–7]. For more complex logical circuits, components called threshold control units (TCUs) [8] have been employed [9–11].

This may seem counterintuitive since throughout the latter half of the twentieth century, we have constructed ever more stable electronic components to be used in computers and other devices. This has been a triumph for electrical engineering and physics. However, not all logical systems are electronic nor man-made [12], and as we may observe, nature is often unstable. As it is easier to study electrical systems, these chaotic logical circuits may help us to better understand naturally occurring logical systems. Furthermore, the chaotic/logical properties of the circuits can be exploited for the purposes of encryption or secure communication.

While there has been an abundance of SPICE simulations and some experimental investigations in the literature, such as [3,9,10], there is a dearth of models for the more complex chaotic logical circuits. This is understandable because the usual modelling techniques become ever more difficult to implement as the number of components increase. Traditionally, logical circuits have been modelled as systems of ordinary differential equations [3,13] because resistors, capacitors and inductors are related via different rates of change. Furthermore, SPICE simulations are often employed as a means of studying circuit designs, but the computational costs become unreasonable as circuits become more complex. However, more recently, there has been some effort in modelling logical circuits as simple discrete dynamical systems [14–16] and developing a mathematical framework for studying chaos in boolean networks [17,18].

To facilitate the development of models of more complex chaotic logical circuits, we created a modelling framework by investigating two chaotic NOR gates and a chaotic set/reset flip-flop (RSFF). We modified the chaotic RSFF/dual NOR gate design of Cafagna & Grassi [11] and simulated our design in MultiSIM (a software based on SPICE) to verify agreement with the PSPICE simulations of [11]. Once the design was satisfactory, we built the circuits and recorded the same measurements as the simulations for the sake of having compatible data sets. These empirical observations and information about the physics from previous investigations were then used to develop the models. This was followed by analysis and simulations of our models, which showed surprising agreement with the experiments and SPICE-based simulations.

As the full schematic of the circuits (3 in 1) is quite complex, and similar to those in the aforementioned works, it is useful to refer to the ‘black box’ schematics of both types of circuits. For example, a NOR gate acts as the negation of the disjunctive operator, i.e. it will output high voltage if and only if it receives low voltage inputs. The RSFF employs two NOR gates with feedbacks as shown in figure 1.

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The body of this work is organized into three main parts: theoretical analyses, experimentation and comparisons between experiments and models. We begin with a discussion of the circuit design and background on Chua’s circuit and TCUs in §2. Section 3 contains the mathematical focus of this article. We first derive deterministic discrete dynamical models for two types of chaotic NOR gates and analyse certain properties of the models including the existence of chaotic dynamics. Then the NOR gate models are used to derive the RSFF model. In §4, we briefly refer to past SPICE simulations and discuss experimental results of our circuit designs. Comparisons between simulations of the deterministic models and experiments in §5 show close agreement in all cases except at clock edges. To rectify the discrepancies during the clock edges a stochastic discrete dynamical model is constructed for the RSFF in §6. This model incorporates races (when two parallel signals do not have the same ‘speed’), which captures more of the clock edge effects than the deterministic model. We end by discussing unexpected predictive capabilities of the models for components that were not explicitly accounted for.

2. Preliminaries

Inventions and innovations of the latter part of the twentieth century have been dominated by electronics and computation. When we think of computation, we generally think of silicon-based devices, and these devices are designed to be as stable as possible, however, nature is often unstable. As it is often easier to physically study electrical systems than logic families arising in nature, studying chaotic logical circuits may help us better understand naturally occurring logical systems. Furthermore, chaotic logical circuits have been used in the design of random number generators, and may be used to design chaotic encryptors/decryptors. If an encryptor is chaotic it would be impenetrable to brute force techniques making for more secure communication.

Before analysing the circuit in question, let us first develop some general ideas about the circuit design. Figure 2 shows the simplified schematics of the two chaotic NOR gates and chaotic RSFF. The NOR and RSFF control the chaotic dynamics of Chua’s circuit (§2a) and exploit it to provide logical outputs. This is done by using one or two TCUs; discussed in more detail in §2b. The TCUs ‘communicate’ with the capacitor voltages via op-amps to create logical outputs: ‘0’ for complete synchronization or a positive difference between the threshold voltage and capacitor voltage and ‘1’ for synchronization with a higher amplitude. Simultaneously, the TCUs create an artificial voltage difference in Chua’s circuit in order to suppress the capacitor voltages to allow stable synchronization.

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It should be noted that the blocks in figure 2 are not absolutely accurate as the block labelled ‘Chua’ has additional op-amps to that of the traditional Chua circuit and feedback from the ‘Chua’ block to the threshold blocks are not explicitly shown. A more detailed schematic of an isolated TCU and capacitor is shown in §2b, and the full schematic of the dual NOR/RSFF is shown in §4b.

(a) Chua circuit

In 1983, Chua developed a simple chaotic circuit using an inductor, two capacitors, a resistor and a nonlinear resistor [5,7,19–21] (figure 3a). When he measured the voltages across the two capacitors and the current through the inductor, he noticed projections of what appeared to be a strange attractor, similar to the Lorenz strange attractor, dubbed the double scroll attractor due to the scroll-like shape (figure 3b). The chaos in the system is produced by perturbations from the nonlinear resistor. In a standard resistor, the ratio between the current through it and the voltage drop across it is proportional with the constant of proportionality being the conductance (the reciprocal of resistance). In a nonlinear resistor, this relationship is as the name suggests: nonlinear. Specifically, in Chua’s nonlinear resistor (called Chua’s diode), the relationship is piecewise linear.

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A year later Matsumoto modelled Chua’s circuit as a system of three ordinary differential equations [4,7,22]. He derived them via Kirchoff’s Laws using the voltage law for the first loop and current law for the nodes on both sides of the standard resistor, which gives us

This system of equations governs the voltages V_C1,V_C2 across the capacitors C₁,C₂ and the current χ_L through the inductor L. A function g(V_C1) represents current coming into the right node of the standard resistor from the nonlinear resistor and G denotes the conductance of the standard resistor.

(b) Threshold control units

It has been shown by Murali et al. [9] that TCUs can be used to manipulate chaotic circuits to produce logical outputs. This was used to simulate the logistic map and a NOR gate. Later Murali et al. [10] designed a similar TCU to be used with Chua’s circuit to implement a single NOR gate. Later Cafagna & Grassi [11] designed two TCUs, similar to that of Murali et al. to be used with Chua’s circuit to implement a RSFF circuit.

In figure 4, we sketch a simplified schematic of a single TCU and capacitor communicating an output through the op-amps. A TCU for chaotic circuits is designed with three guiding principles, which are outlined in the context of figure 4:

• — If the capacitor voltage V_C is less than or equal to the threshold voltage V_T, the TCU does not affect the chaotic circuit. If V_C>V_T, a voltage difference of V_T is imposed on the chaotic circuit.

• — If V_C≤V_T, the relevant op-amp outputs U=0. If V_C>V_T, we have U=V_C−V_T.

• — When both inputs are unity (e.g. I₁=I₂=1), V_T=V_C while V_C is allowed to vary freely.

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The TCUs for the Murali et al. [10] NOR gate, Cafagna & Grassi [11] RSFF and our circuit sets a base threshold voltage of V_T(0,0) such that the capacitor voltage V_C remains at a fixed point of V_C* when V_T(0,0) is imposed on Chua’s circuit; i.e. V_C(V_T(0,0))≈V_C* and V_C(V_T>V_T(0,0))≤V_T. The value V_C* is then used as a logical ‘1’. It should be noted that V_C does not depend only on V_T, however, Chua’s circuit can be reverse engineered to find a V_T that forces V_C to be approximately fixed.

3. Deterministic models

The dynamics of the TCUs are studied first with a focus on modelling them as discrete dynamical systems. We postulate tent map-like behaviour of the threshold voltages, which is reasonable in the physical sense since our op-amps influence the signal in an approximately piecewise linear manner. Furthermore, the NOR gate developed by Murali et al. [9] employed a TCU designed to simulate a logistic map, and a tent map is topologically conjugate to a logistic map. While our TCUs behave somewhat differently from that of Murali et al. the underlying effects will be similar.

One may suggest solving Matsumoto’s equation [4] for Chua’s circuit as part of the model. While this would be a legitimate approach, the goal of the article is to formulate the simplest model in terms of derivation and simulation. Having to solve the ordinary differential equation at each time step would be reasonable for a two-gate circuit, but would not be scalable to large chaotic logical circuits with many gates. For these reasons, we forgo explicitly modelling the capacitor voltages, and instead develop models for the threshold voltages and the outputs, then show that the derived capacitor voltages agree reasonably well with experiments and MultiSIM simulations in addition to showing the threshold and outputs agree surprisingly well with the experiments and simulations.

We first model the NOR gates, then we use those models to construct the RSFF model. This is accomplished by employing continuous extensions and approximating the behaviour of the TCU and Chua’s circuit. Simplified schematics of the NOR gate and RSFF (figure 2 in §2) help illustrate the modelling process. It should be noted that while in the experiments we use a high voltage of 1.84 V, in our models this is normalized to 1.

(a) NOR gate

Here, we derive and analyse the NOR gate models. While the full schematic of the gates are given in §4, these may be simplified to figure 2a in order to get a general picture of the circuit.

(i) Derivation

We begin by formulating the simplest continuous extension of the NOR operator: $x\overline{\vee }y=(1-x)(1-y)$. This gives us the equation,

where U are the respective outputs and I are the respective inputs as shown in figure 2a. This naive extension is enough to approximate the behaviour for the NOR gate outputs, and we shall also modify them later to simulate certain subtle aspects of the circuit. However, the more interesting dynamics are observed in the TCUs.

First, let us define the maps representing the threshold voltages, $f:{[0,1]}^2\times [-2,2]\to [-2,2]$ and $g:{[0,1]}^2\times [-1,1]\to [-1,1]$, where the chosen intervals are the operating domains of the TCUs by design. We apply these maps to the inputs and current time threshold voltages to get the next time threshold voltages,

where ξ and η are the respective threshold voltages as shown in figure 2a.

As discussed in §2b, the TCUs are designed to set a base threshold voltage of ξ_*=f(0,0,ξ_*) and η_*=g(0,0,η_*) such that the two capacitor voltages remain fixed. These base threshold voltages are f(0,0,0)=0 and g(0,0,−1)=−1. Furthermore, when either I₁ or I₂ are unity, a normalized voltage of unity is added to the base threshold voltage, and when both are unity the threshold voltage synchronizes with the capacitor voltage, which varies in a chaotic fashion, denoted by a star (⋆). These design features and observations are used to formulate functions f and g that produce the expected behaviour, a summary of which is tabulated in (3.3).

To satisfy these criteria, we first define the maps, $y_f:[-2,2]\to [-2,2]$ and $y_g:[-1,1]\to [-1,1]$, then

satisfies each property except chaotic behaviour.

Now, we must formulate y_f and y_g such that (3.4) reproduces the qualitative behaviour of the threshold voltages for (I₁,I₂)=(1,1) and (I₃,I₄)=(1,1) as will be shown in §4. Intuitively, we know by design that the set of iterates of y_f ‘chaotically orbits’ two fixed points (plus and minus unity) and that of y_g ‘chaotically orbits’ one fixed point (the origin). The maps will also have an extra fixed point (a source) as we will show in the analysis. As mentioned previously, we postulate y_f and y_g will be tent map-like, which is reasonable in the physical sense since these op-amps influence the signal in an approximately piecewise linear manner. For y_f we write,

and we write y_g as, We illustrate (3.5) and (3.6) in figure 5. In figure 5a and (3.5), μ_f is the slope of the middle line segment and it also determines the slope of the other two line segments, whereas ν_f mainly affects the domain of the map. In figure 5b and (3.6), μ_g is twice the height of the map and 1−ν_g is the amount the new interval is translated from the interval [0,1]. Moreover, all parameters are positive.

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This gives us a model of the thresholding in the dual NOR gate operation of the circuit.

(ii) Basic properties

As the interesting behaviour arises for (I₁,I₂)=(1,1) and (I₃,I₄)=(1,1), it suffices to analyse f(1,1,x) and g(1,1,x). First, we search for the fixed points. From empirical observations, we require g(1,1,x) and f(1,1,x) to have a fixed point at the origin and f(1,1,x) to have two other non-zero fixed points. By definition, the latter has a fixed point at the origin and two non-zero fixed points. However, for the former, we require the right branch to intersect the origin. To achieve this, we set g(1,1,x)=x=0 for x∈[ν_g−1/2,ν_g](the right branch),

Furthermore, in order to ensure the inequality, ν_g−1/2≤x≤ν_g, we require ν_g≤1/2, i.e. μ_g≥1.

Now let us identify any additional fixed points for g(1,1,x), which necessarily lies on the left branch, i.e. x∈[ν_g−1,ν_g−1/2],

Next, we identify the two non-zero fixed points for f(1,1,x). For x∈[±ν_f,±ν_fμ_f],

For the sake of convenience, we outline the fixed points in table 1.

To analyse the stability of the fixed points of g(1,1,x), let us take the derivative,

Both fixed points are sources when μ_g>1. For μ_g=1, there is a line of fixed points on the left branch such that it constitutes a global attracting set. Clearly, this case is unphysical, and hence we require μ_g>1.

Taking the derivative for f(1,1,x) gives,

By definition, μ_f≥1, since otherwise the two outer branches would be undefined. If μ_f=1, there is a line of fixed points on the middle branch, and hence this too is unphysical. Therefore, we require μ_f>1, which shows the origin is a source. For the other two fixed points, if (1+μ_f)/(1−μ_f)<−1 they are sinks and if (1+μ_f)/(1−μ_f)>−1 they are sources. Notice that (1+μ_f)/(1−μ_f)=−1 only when μ=0, which we showed was impossible. Now, if (1+μ_f)/(1−μ_f)<−1, 1<−1, which is false. If (1+μ_f)/(1−μ_f)>−1, 1>−1, which is true. Therefore, these fixed points are always sources.

The fixed points along with the conditions on the parameters required to yield physical results are summarized in table 1.

(iii) Chaos

Here, we shall prove the maps g(1,1,x) and f(1,1,x) become chaotic for certain parameters. First, we prove this for g(1,1,x), which employs a simple translation to the tent map.

Theorem 3.1

The map g(1,1,x) is chaotic for μ_g≥2. In addition, it has a non-wandering set in the form of a translated Cantor set on [1−ν_g,ν_g] for μ_g>2. Moreover, for μ=3, the non-wandering set is the middle-third Cantor set translated to the interval [1−ν_g,ν_g].

Proof.

Consider the translation $(u,v)=H(x,y):\hspace{0.17em}{[1-{\nu }_g,{\nu }_g]}^2\to {[0,1]}^2$, defined as (u,v)=(x+1−ν_g,g(1,1,x)+1−ν_g), applied to g(1,1,x). This produces the map $v=T_{{\mu }_g(u)}:\hspace{0.17em}[0,1]\to [0,1]$, which is exactly the tent map. As H is a homeomorphism, it suffices to analyse the tent map. It is well known that when μ≥2, the tent map is chaotic. Furthermore, for μ>2, the non-wandering set is a Cantor set, and for μ=3, it is precisely the middle-third Cantor set. This shows the map g(1,1,x) is also chaotic for μ_g≥2, and has a non-wandering set in the form of a translated Cantor set, thereby completing the proof. ▪

Now we prove f(1,1,x) is chaotic in the physical parameter regime outlined in table 1. For the sake of brevity, we assume the parameters are in this regime for our next theorem. The main idea of the proof is to search for 3-cycles and use the main theorem by Li & Yorke [23]. As the formula for f³ becomes overly complex, we shall use properties of f³ to show the existence of a 3-cycle rather than finding it explicitly, and we provide visual aids to illustrate the proof.

Theorem 3.2

For every$n\in \mathbb{N}$there exists a periodic point p_n∈[−μ_fν_f,μ_fν_f] of the map f(1,1,x) having period n and [−μ_fν_f,μ_fν_f] contains chaotic orbits of f. Furthermore, there exists an uncountable set S⊂[−μ_fν_f,μ_fν_f] containing no periodic orbits.

Proof.

It is shown in [23] that a 3-cycle implies chaos. Now, we show there exists a 3-cycle for all parameter values in the physical regime. This is done by finding the roots of f³ not including the fixed points, or rather showing they exist.

First, let P_n be the set of roots of fⁿ, then P₃∖P₁ (all points in P₃ not in P₁) is the set of points having period 3. Now we may analyse the cardinalities (card) of the sets of intersection points. We observe f³ (figure 6) has 17 linear branches. As these are linear, each branch may intersect the line y=x at most once. The two outermost branches will never intersect the line y=x for the parameter regime outlined in table 1. Then $max(\mathbf{\text{card}}(P_3))=15$ and card(P₁)=3 (i.e. f has three fixed points), hence $max(\mathbf{\text{card}}(P_3\setminus P_1))=12$. Notice, a 3-cycle exists only if card(P₃∖P₁)∈{6,12} due to the symmetry.

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We observe (figure 6a) card(P₃∖P₁)=12 for the parameters near that used in simulations. If μ_f and ν_f are varied forward we maintain card(P₃∖P₁)=12. If we vary them backward, the first instance card(P₃∖P₁)≠12 occurs when the cusps of the second and third branches from the left, and, respectively, from the right, lie on the line f(1,1,x)=x. The cusps are located at

Then, solving $\hat{x}=f(1,1,\hat{x})$ for μ_f, gives μ_f=1, which is unphysical. As card(P₃∖P₁)=12 in the parameter regime of table 1, 3-cycles (in fact, four of them) exist. Therefore, the hypotheses of [23] is satisfied, thereby completing the proof. ▪

(b) Set/reset flip-flop

Now that we have a model for the NOR gates we can derive the model of the RSFF. Just as with the NOR gate, we refer to the simplified schematic of the RSFF in figure 2b. For the traditional RSFF, the outputs from each NOR gate is fed back into the other. Therefore, we replace I₁ and I₃ with R and S and I₂ and I₄ with Q and Q′ in (3.4) and (3.1) to get

and It should be noted that (3.9) must be used in conjunction with (3.2). These models are simulated in §5.

4. Experiments and SPICE simulations

In this section, we discuss previous PSPICE simulations for chaotic NOR gate and RSFF constructions and present our own design and experimental results to demonstrate the robustness of the circuit design even in the midst of chaos.

(a) Previous investigations

Murali et al. developed and tested a chaotic NOR gate construction in [9] and with more detail in [10]. Then Cafagna & Grassi [11] designed an RSFF using similar principles to the NOR gate of Murali et al. which is now the inspiration for our own RSFF.

The RSFF is designed with Chua’s circuit at its core and two TCUs to realize each NOR gate. Two switches are used to convert the circuit from operating as two separate NOR gates to operating as an RSFF and vice versa. Cafagna and Grassi provide plots of the inputs, outputs and threshold voltages for both NOR gates, the inputs and outputs of the RSFF, and finally the voltages across the two capacitors. We recreate the same types of plots for our design in order to facilitate comparisons.

(b) NOR/RSFF design

As the circuit of Cafagna & Grassi [11] uses components that have become unavailable, we needed to design a modern chaotic RSFF/dual NOR gate. The schematic of our circuit design is shown in figure 7.

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For the MultiSIM simulations (figure 8), we use the components shown in table 2. The chaotic backbone of the circuit comes from Chua’s circuit, and we employ TCUs to produce the logical outputs. The MultiSIM plots for the dual NOR gate are shown in figure 8. We then made a physical realization of the circuit with mostly the same components (table 2) as the MultiSIM simulations.

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(c) Experiments

The experimental set-up is shown in figure 9. To power the circuit and get readings we used a DC power supply, wave form generator, Arduino Due^®, and an oscilloscope. From the physical realization, we reproduced the MultiSIM plots. To activate the dual NOR gate, we keep switches 1 and 2 in figure 7 closed and switches 3 and 4 open.

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The experimental results for the dual NOR gate set-up are shown in figure 10. In figure 10c,d, we notice windows of what looks like chaotic dynamics. This is also observed in the MultiSIM simulations. It should be noted that the threshold behaviour of the MultiSIM circuit and the physical realization are slightly different due to a change in op-amps.

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To deactivate the dual NOR gate we open switches 1 and 2 in figure 7. To properly activate the RSFF we need to close switches 3 and 4, however, we get the RSFF outputs even with the switches open. When we close the switches we notice the race conditions for the ‘1–1’ input causing wild oscillations, which is completely missed in the simulations. This shows that the design has implicit feedbacks, through the op-amps, which results in RSFF operations. However, when the two NOR gates are explicitly connected with one another (i.e. the output of one NOR gate feeds back to the input of the other NOR gate) the race condition exacerbates the oscillations. The experimental results for the RSFF set-up are shown in figure 11. While the experiments of the RSFF mainly work as expected, the MultiSIM simulations are not able to properly capture this behaviour, which shows the necessity of other modelling techniques.

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5. Comparison between deterministic models and experiments

From the models in §3, we can simulate the NOR gate and RSFF operations. The codes for the simulations are quite simple with the majority of it dedicated to iterating (3.2) for both operations. For both the NOR gate and RSFF, we assume there is a ‘circuit frequency’, which we define as the amount of time it takes a signal to traverse the entire circuit, and is on the order of 100 μs. We also set the following parameters: μ_f=3.2, ν_f=0.5694, μ_g=2 and ν_g=1/3.

Furthermore, for the NOR gate, while the model is not stochastic (no added noise), we do make small deterministic perturbations in the inputs to approximate the effects of noise and demonstrate sensitivity to initial conditions. For I₂ and I₄, from the 20 ms mark to the 40 ms mark we add 10⁻⁹, and from the 60 ms mark to the 80 ms mark we subtract 10⁻⁹. This equates to less than a nano-volt difference (recall the voltage used in the experiments is 1.84 V). The simulations are plotted in figure 12.

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Notice, we have surprisingly close agreement with figure 10. The model even replicates the lag observed in the second threshold (in figure 10 the second threshold voltage seems to remain close to zero for a few milliseconds). The only dynamics that were missed are the effects on the outputs at the clock edges. This shall be rectified in the sequel.

For the RSFF, we employ the same circuit frequency and perturbation on the initial conditions. This is plotted in figure 13a. Moreover, in the circuit design, the outputs are achieved by taking the difference between the voltage across the capacitors and their respective threshold voltages. However, we approach this from the other direction where we have a model for the outputs and threshold voltages and take the sum to predict the voltage across the capacitors. As our system is discrete and the phase plane of Chua’s circuit is continuous, we interpolate between the respective points. While this is not perfectly accurate, it illustrates a more complete picture of the dynamics than the purely discrete case. This is plotted in figure 13b.

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Again, as with the NOR gate, we are able to reproduce the behaviour for the RSFF except for the clock edge effects. We also plot the iterate plane for the capacitor voltages. This can be thought of as iterates of a Poincaré map of the double scroll attractor. After interpolating between the iterates, we observe a double scroll-like projection in the plane. However, it is not exactly a double scroll projection, nor can it be due to the artificial interpolation.

6. Stochastic model for set/reset flip-flop

It is evident that the deterministic models miss some of the more subtle clock edge effects, which we endeavour to rectify here.

(a) Derivation

Now let us rectify the discrepancies between figures 12, 13a and figures 10, 11. Physically, the oscillations observed at certain clock edges are caused by a non-binary difference in the capacitor voltage and threshold voltage (recall that the outputs are calculated by subtracting the threshold voltage from the capacitor voltage). However, we take a different approach, developing a model for the threshold voltages and output voltages rather than determining the output voltages via the other two as explained in §3. To accomplish this, we must still rely on the physical intuition of the thresholding mechanism.

Whenever the inputs are such that they cause a threshold to change its state drastically (not including the gradual transition to chaos), the TCU attempts to synchronize the capacitor voltage with the threshold voltage for the proper output. This causes a competition between the capacitor voltage (under the influence of the previous input) and the TCU (stimulated by the current input), which the TCU finally wins. During this process, due to the chaotic nature of both the capacitor voltages and threshold voltages, each path to synchronization is different. As we do not have the explicit model for the capacitor voltages, we will treat this competition as a stochastic process.

During the transitions that lead to the edge effect, we assume there is a probability at each time step that the output will either accept the new inputs or be induced by the weighted average of inputs from previous time steps, where the weights are also determined randomly (or rather, pseudorandomly). Here, we define time step as the reciprocal of the circuit frequency.

Consider the sequences ${\{m\}}_1^M$, ${\{n\}}_0^N$ and ${\{t\}}_0^T$, such that T=N+1 and M=T. Let N be the number of time steps in the past that affect future outcomes and T be the number of time steps after the edge that the output is affected (usually approx. 1 ms). Further, let $\{w_j^{(t)},\dots ,w_j^{(t-n+1)},w_j^{(t-n)},w_j^{(t-n-1)},\dots ,w_j^{(t-N)}\}\subseteq {\{m\}}_1^M$ be the weights applied, with the same probability, out of ${\{m\}}_1^M$, to the respective inputs, $I_j^{(t-n)}$ for j={1,2,3,4}. Let p(t)={0,1} be some random variable for each time t, with not necessarily identical distributions. In addition, let

be the perceived input. Then we substitute $A_j^{(t)}$ into (3.1) for the respective inputs, to model the effects at the transition points. It should be noted that besides the transition points, which last about a millisecond, the outputs behave as described by the continuous extensions. Finally, to simulate noise produced by the wave generator, we add/subtract a small random term, $ϵ\in \mathbb{R}$, to the inputs (i.e. $I_j\to I_j+ϵ$).

For the RSFF, we use the same technique, except this time we plug (6.1) in only for the R and S. Hence, for the transitions, (3.10) becomes

(b) Comparison with experiments

To simulate the models, we use the same values for parameters in y_f and y_g, and for the circuit frequency, as in §5. For the NOR gate and RSFF, we set M=N+1=T=11 (i.e. approx. 1 ms) and ϵ=±O(10⁻⁸). The choice of ϵ describes a physical signal which has less than 1 nV of noise, on average. The simulations for the NOR gate are plotted in figure 14. We observe that these are precisely the type of damped oscillations seen in figure 10.

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The RSFF and capacitor voltage simulations are plotted in figure 14a,b, respectively. Observe that the oscillations match the type in figure 11b. Furthermore, figure 15b is now qualitatively more similar to figure 10b.

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7. Conclusion

In the context of chaotic logical circuits there have been many SPICE simulations, some experiments, and only a few models. Simpler chaotic logical circuits are modelled as ordinary differential equations [3,13]. More complex ones are generally studied using SPICE simulations [9–11] and physical realizations [9,10]. We studied the RSFF/dual NOR gate through experiments, dynamical modelling, simulations and analysis of the models.

By modifying the circuit in [11], we designed an RSFF/dual NOR gate using modern components. We then simulated the circuit using MultiSIM to confirm the new design produces the proper outputs. Next, we put together a physical realization of the circuit and conducted experiments to show agreement with MultiSIM. By observing the behaviour of the circuit and using properties of TCUs as seen in [9,10], we are able to model the dynamics of the circuit as difference equations. The chaotic behaviour of the models is verified by standard dynamical systems analysis for one-dimensional maps. Finally, we simulate our models to show agreement with both experiments and MultiSIM. It was expected that the original deterministic models would not be sufficient to replicate the ‘race’ behaviour observed in the outputs. Therefore, we inserted probabilistic elements to show this edge-trigger phenomenon, thereby deriving a stochastic model.

While we are able to capture much of the dynamics, there is a need for more sophisticated models to replicate the more complex ‘race’ behaviour. Furthermore, as this is a rich problem, and we have a physical realization, many new phenomena may arise. It shall be useful to study various physical bifurcations as we make changes in the circuit and make connections with topological bifurcations. We predict this will lead to local bifurcations such as transcritical, pitchfork and Neimark–Sacker as observed in other models [16,18], and novel global bifurcations previously unobserved in the literature. We shall also endeavour to build other more complex circuits to study analogues of other logic families and exploit the chaotic and logical properties for the purposes of encryption and secure communication.

Data accessibility

The data for the experiments are provided in text. All of the codes used in the simulations are available as the electronic supplementary material.

Authors' contributions

A.R. and D.B. conceived the ideas and developed the theory. A.R. designed the experiments. I.J. conducted the experiments. All authors contributed in writing/editing and gave their final approval for publication.

Competing interests

We have no competing interests.

Funding

I.J. was funded by the NJIT URI phase-1 and phase-2 undergraduate student seed grants with A.R. as graduate student mentor and D.B. as faculty mentor.

Footnotes

Electronic supplementary material is available online at http://dx.doi.org/10.6084/m9.figshare.c.3980796